How Do I Set Up and Enable the A7’s Memory Protection Unit (MPU) and Cache?

The A7’s memory protection unit (MPU), shown in Figure 1, supports up to eight separate memory regions, each with individual sizes, privileges, and cache settings.

Figure 1.  The A7’s Memory Protection Unit (MPU).

The A7 Hardware Abstraction Layer (A7HAL), which is part of the Triscend Software Development Kit (SDK), includes convenient routines for initializing and enabling the A7’s MPU and cache.

NOTE

The Triscend SDK and A7HAL are available for download from the Triscend web site.

    http://www.triscend.com/products/TextEvalDL.htm#SDK

To use the A7HAL, be sure to include it as part of your main program.

#include <a7hal.h>

NOTE

The following example is based on the MPU example application included with the Triscend SDK.  After installing the SDK in the default location, you can find the sample application in the following directory.

    C:\Triscend\SDK_1.0.3\Triscend\a7hal\examples\mpu

First, declare a structure that defines the MPU settings.  The A7HAL has a pre-defined structure called a7hal_mpu_map.  In the structure, declare the following attributes for each of the eight protected regions.  Region 7 has the highest priority and Region 0 the lowest.

a7hal_mpu_map myMap[] = {
/*
 * base        size             permissions     cacheEnable
 */

 

  /* From Region 7 down to Region 0 */

  /* Enable access to first 32MB of address space */
  {0x00000000, A7HAL_SIZE_32MB, A7HAL_SUP_RW_USR_RW, YES},

   
  /* Enable access to first 4MB of SDRAM */       

  {0xc0000000, A7HAL_SIZE_4MB, A7HAL_SUP_RW_USR_RW, YES},

 

  /* Enable access to first 2MB of FLASH */ 
  {0xd0000000, A7HAL_SIZE_2MB, A7HAL_SUP_RW_USR_RW, YES},

 

  /* Enable access to 64KB for A7’s control registers */ 
  {0xd1010000, A7HAL_SIZE_64KB, A7HAL_SUP_RW_USR_RW, NO},

 

  /* Enable access to the 16KB for A7’s internal SRAM */   
  {0xd1030000, A7HAL_SIZE_16KB, A7HAL_SUP_RW_USR_RW, NO},   

 

  /* Enable access to 1MB region for memory-mapped CSL

     registers.  These registers cannot be cached */

  {0x10000000, A7HAL_SIZE_1MB, A7HAL_SUP_RW_USR_RW, NO},

 

  /* Empty region */

  {0x00000000, 0, 0, NO},

 

  /* Empty region */

  {0x00000000, 0, 0, NO},


};

 

After setting up the MPU, create a routine to handle any memory aborts.  A memory abort occurs when the A7 attempts a transaction to a region in memory not defined by one of the MPU’s memory areas, as shown in Figure 1.  If such a transaction occurs, decide how you wish to handle this condition.

In this simple example, the memory abort handler reports the error and continues with the next instruction.  The next instruction executed depends on whether the handler is compiled in ARM or Thumb mode.

/*

 *  Abort Interrupt Handler

 */

void abortHandler( unsigned long Addr )

{

  printf("Abort exception at address 0x%08x\n", Addr);

#ifdef __THUMB__

  printf("Program continues at address 0x%08x\n", Addr + 2);

#else

  printf("Program continues at address 0x%08x\n", Addr + 4);

#endif

}

 

Finally, in your main program, initialize the memory abort handler and then program and enable the MPU.

/*

 *  MAIN FUNCTION

 */

int main(  )

{

    /* Initialize the memory abort handle created above */

    a7hal_icu_setUserAbort( abortHandler );

 

    /* Program the settings into the MPU */

    a7hal_mpu_setMap( myMap );

    /* Enable the map */

    a7hal_mpu_enableMap(  );

 

    printf( "So far so good...\n" );

 

    /* Create a pointer that points to an unspecified area

       in memory */

    int *Pointer = ( int * ) 0x20000000;

   

    /* This next line causes an abort exception because the

       transaction is to a memory location not specified in

       the MPU settings  */

    *Pointer = 0x55aa55aa;

 

    printf( "Done\n" );

 

    /* Never return from main */

    while (1) ;

 

/* end main.c */

 

Base Address

Figure 2 shows the A7’s memory map after initialization.  The addresses along the left show the base address for various features in the memory map.  The numbers to the right of each region show its size.

 

Figure 2.  The A7’s Memory Map after Initialization.

Area Size

The size for each protected area can range from 4KB up to 4GB.  The A7HAL provides enumerated values to specify the area size, as shown in Table 1.

Table 1.  Enumerated Values for Area Size.

Area Size

Enumerated Value

Value

4 KB

A7HAL_SIZE_4KB

0x0b

8 KB

A7HAL_SIZE_8KB

0x0c

16 KB

A7HAL_SIZE_16KB

0x0d

32 KB

A7HAL_SIZE_32KB

0x0e

64 KB

A7HAL_SIZE_64KB

0x0f

128 KB

A7HAL_SIZE_128KB

0x10

256 KB

A7HAL_SIZE_256KB

0x11

512 KB

A7HAL_SIZE_512KB

0x12

1 MB

A7HAL_SIZE_1MB

0x13

2 MB

A7HAL_SIZE_2MB

0x14

4 MB

A7HAL_SIZE_4MB

0x15

8 MB

A7HAL_SIZE_8MB

0x16

16 MB

A7HAL_SIZE_16MB

0x17

32 MB

A7HAL_SIZE_32MB

0x18

64 MB

A7HAL_SIZE_64MB

0x19

128 MB

A7HAL_SIZE_128MB

0x1a

256 MB

A7HAL_SIZE_256MB

0x1b

512 MB

A7HAL_SIZE_512MB

0x1c

1 GB

A7HAL_SIZE_1GB

0x1d

2 GB

A7HAL_SIZE_2GB

0x1e

4 GB

A7HAL_SIZE_4GB

0x1f

Permissions

Each protected area can grant separate read and write privileges to the supervisor and user modes.  The A7HAL provides enumerated values to specify the permissions, as shown in Table 2.

Table 2.  Enumerated Values for Area Permissions.

Supervisor Access

User Access

Enumerated Value

Value

None

None

A7HAL_SUP_NO_USR_NO

0x00

Read/Write

None

A7HAL_SUP_RW_USR_NO

0x01

Read/Write

Read Only

A7HAL_SUP_RW_USR_RO

0x02

Read/Write

Read/Write

A7HAL_SUP_RW_USR_RW

0x03

 

 

SDK: 1.0.3

This solution may or may not apply to other versions of the FastChip development system.

 

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